ESA Intended Invitation To Tender

18.1TT.87


Title: LOW PHASE NOISE PHASE LOCKED LOOP FOR HIGH-THROUGHPUT SATELLITES (ARTES AT 5C.387) (ON DELEGATION REQUEST)
Program ref.: CC for Advanced Tech
Tender Type: C
Quarter: 184
Tender Status: INTENDED
Price Range: > 500 KEURO
Budget Ref.: E/0505-01C - CC for Advanced Tech
Proc. Prop.: DIPC
Special Prov.: BE+DK+FR+DE+IT+NL+ES+SE+CH+GB+IE+AT+NO+FI+PT+GR+LU+CZ+RO+CA
Establishment: ESTEC
Directorate: Directorate Telecom & Integrated Applica
Department: Telecom Technologies,Product&Systems Dep
Division: Technologies and Products Division
Responsible: Schmitt, Dietmar
Products: Satellites & Probes / Electronics / EEE Components / Monolithic Microcircuits (including MMICs)
Techology Domains: RF Systems, Payloads and Technologies / RF Technologies and Equipment / Time and Frequency
Industrial Policy Measure: C1 - Activities in open competition limited to the non-Larg...
Publication Date: 07-JAN-19

Objective: The objective of this activity is to design, manufacture and test a single chip phase locked loop with less than 100 fs jitter for on-board High Throughput Satellites. Targeted Improvements: - Improvement of the phase noise by 10 dB and drastic reduction of spurious signals compared to state-of-the-art architectures; - Adding frequency agility to local oscillators without sacrificing the phase noise performance needed to support high order modulation schemes. Description: Satellites making use of Q- and V- bandfeeder links and higher order modulation schemes require high frequency local oscillators (in the order of 30 GHz or more) with highspectral purity. Today, single chip frequency synthesisers operating at 30 GHz and above are not available in Europe. Advances in digital frequency synthesis for 5G terrestrial applications are paving the way to achieving low power consumption (< 100 mW instead of0.5 W and above) and low jitter in combination with reduced spurious outputs (< -60 dBc) at millimetre wave frequencies. Adding frequency agility to local oscillators without sacrificing the phase noise performance needed to support high order modulation schemesis now possible. In this activity, an engineering model of a single chip European synthesiser suitable for use in high throughput satellite applications shall be designed manufactured and tested. The synthesiser shall be capable of generating a millimetre wave frequency with less than 100 fs jitter and with spurious signal content below -60 dBc. footnote: On Delegation Request (formerly calledPriority 2) activities will only be initiated on the explicit request of at least one National Delegation. Procurement Policy: C(1) = Activity restricted to non-prime contractors (incl. SMEs). For additional information please go to EMITS news "Industrial Policy measures for non-primes, SMEs and RD entities in ESA programmes".